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Jiancheng Xue authored
The CRG(Clock and Reset Generator) block provides clock
and reset signals for other modules in hi3519 soc.

Signed-off-by: default avatarJiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
6c9da387
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